1. Field Of The Invention
This invention relates to memory arrays and, more particularly, to apparatus for increasing the speed of erase and programming operations in a flash electrically erasable programmable read only memory (flash EEPROM) array.
2. History Of The Prior Art
Modern computer systems make extensive use of long term memory. Typically this memory is provided by one or more electro-mechanical hard (fixed) disk drives constructed of fiat circular magnetic disks which rotate about a central axis and which have a mechanical arm to write to or to read from positions on the magnetic disk. Hard disk drives are very useful and have become almost a necessity to the operation of personal computers. However, such electro-mechanical drives are relatively heavy, require a significant amount of space within a computer, require a significant amount of power in use, and are very susceptible to shock. A hard drive within a portable computer which is dropped is quite likely to cease functioning with a catastrophic loss of data.
Recently, forms of long term storage other than electro-mechanical hard disk drives have become feasible for use in computers. One of these is flash EEPROM. A flash EEPROM memory array includes a large plurality of floating-gate field effect transistors arranged as memory cells in typical row and column fashion with circuitry for accessing the individual cells and placing the memory transistors of those cells in one of two memory conditions. A flash EEPROM memory cell, like a typical EPROM cell retains information when power is removed. Unlike a typical EPROM cell, however, a flash EEPROM cell may be erased electrically in place within a system.
Flash EEPROM memory has a number of characteristics which adapt it to use as long term memory. It is light in weight, occupies very little space, and consumes less power than electro-mechanical disk drives. More importantly, it is especially rugged. It will withstand without adverse effects repeated drops each of which would destroy a typical electro-mechanical hard disk drive.
A difficulty with flash EEPROM, however, is that it must be erased before it can be reprogrammed and it is very slow to erase. Flash EEPROM is erased by applying a high voltage simultaneously to the source terminals of all of the transistors (cells) used in the memory while the other terminals are suitably biased. Because these source terminals are all connected to one another by metallic busing in the array, the entire array must be erased at once. While an electro-mechanical hard disk drive will typically store information in a first area of the disk and then rewrite that same area of the disk when the information changes by changing the magnetic fields stored in the area, this is not possible with a flash memory array without erasing all of the valid information that remains in the array along with the invalid (dirty) information.
Because of this, a different arrangement is used for erasing dirty sectors of a flash EEPROM array. One such arrangement is disclosed in detail in U.S. patent application Ser. No. 07/969,131, entitled A Method and Circuitry for A Solid State Memory Disk, S. Wells et al, filed on Oct. 30, 1992, and assigned to the assignee of the present invention. First, the entire array is divided into smaller separately erasable blocks so that when a block is erased the amount of valid data which must be reprogrammed is reduced. Typically, the array is composed of a number of silicon chips; and each such chip includes a number of such blocks. Then, when the information at a data entry changes, the changed information is written to a new sector on an available block rather than written over the old data; and the old data is marked dirty. After some period, the management processes controlling the block will determine that it is necessary to release space tied up in dirty sectors and select a block to clean up. When cleanup occurs, all of the valid data in the selected block is first written to a new block with free space; and then the dirty block is erased and put back into use as a clean block of memory. Because of this involved process, it typically takes as much as two seconds to clean up a block of a flash EEPROM array. However, because erasure need not occur with each entry which is rewritten, erasure may be delayed until a block contains a sufficient amount of dirty information that cleanup is feasible. This reduces the number of erasure operations to a minimum and allows erasure to occur in the background when the facilities for controlling the array are not otherwise occupied with reading and writing.
Even though the erasing and attendant clean up processing may be accomplished in the background, it is desirable to accelerate as much as possible these and other operations of a flash EEPROM array which is used as long term memory. It has been discovered that a substantial problem affecting the speed of erasure of a flash EEPROM array is that the processes for manufacturing such products produce blocks of memory which require as much as three times the typical time in order to erase. These same blocks appear to exhibit the same slow switching speed when being programmed. Since the entire memory array is required to provide sufficient switching time that its slowest block of memory will respond, the entire array must switch at the slower speeds required by the slowest blocks in programming and erasure. It is desirable to improve the rate of switching of those blocks of a flash EEPROM array which are slower to erase and program so that the speed of the memory array may be improved.